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<article article-type="research-article" dtd-version="1.3" xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink" xmlns:xsi="http://www.w3.org/2001/XMLSchema-instance" xml:lang="ru"><front><journal-meta><journal-id journal-id-type="publisher-id">radioelectronics</journal-id><journal-title-group><journal-title xml:lang="ru">Известия высших учебных заведений России. Радиоэлектроника</journal-title><trans-title-group xml:lang="en"><trans-title>Journal of the Russian Universities. Radioelectronics</trans-title></trans-title-group></journal-title-group><issn pub-type="ppub">1993-8985</issn><issn pub-type="epub">2658-4794</issn><publisher><publisher-name>Saint Petersburg Electrotechnical University</publisher-name></publisher></journal-meta><article-meta><article-id pub-id-type="doi">10.32603/1993-8985-2025-28-1-17-34</article-id><article-id custom-type="elpub" pub-id-type="custom">radioelectronics-967</article-id><article-categories><subj-group subj-group-type="heading"><subject>Research Article</subject></subj-group><subj-group subj-group-type="section-heading" xml:lang="ru"><subject>ПРОЕКТИРОВАНИЕ И ТЕХНОЛОГИЯ РАДИОЭЛЕКТРОННЫХ СРЕДСТВ</subject></subj-group><subj-group subj-group-type="section-heading" xml:lang="en"><subject>ENGINEERING DESIGN AND TECHNOLOGIES OF RADIO ELECTRONIC FACILITIES</subject></subj-group></article-categories><title-group><article-title>Вероятностный подход к оценке качества проведения операции фотолитографии при производстве печатных плат</article-title><trans-title-group xml:lang="en"><trans-title>Probabilistic Approach to Assessing Photolithography Quality in the Production of Printed Circuit Boards</trans-title></trans-title-group></title-group><contrib-group><contrib contrib-type="author" corresp="yes"><contrib-id contrib-id-type="orcid">https://orcid.org/0000-0001-7686-6300</contrib-id><name-alternatives><name name-style="eastern" xml:lang="ru"><surname>Коробков</surname><given-names>М. А.</given-names></name><name name-style="western" xml:lang="en"><surname>Korobkov</surname><given-names>M. A.</given-names></name></name-alternatives><bio xml:lang="ru"><p>Коробков Максим Андреевич – магистр по направлению "Информатика и вычислительная техника" (2021), старший преподаватель и аспирант кафедры "Цифровые технологии и информационные системы"</p><p>Волоколамское шоссе, д. 4, Москва, 125993 </p></bio><bio xml:lang="en"><p>Maksim A. Korobkov, Master in Informatics and Computer Science (2021), Senior Lecturer and Postgraduate Student of the Department of Digital Technologies and Information Systems</p><p>4, Volokolamskoe highway, Moscow 125993 </p></bio><email xlink:type="simple">josef_turok@bk.ru</email><xref ref-type="aff" rid="aff-1"/></contrib><contrib contrib-type="author" corresp="yes"><contrib-id contrib-id-type="orcid">https://orcid.org/0009-0005-8653-8702</contrib-id><name-alternatives><name name-style="eastern" xml:lang="ru"><surname>Барабанов</surname><given-names>В. С.</given-names></name><name name-style="western" xml:lang="en"><surname>Barabanov</surname><given-names>V. S.</given-names></name></name-alternatives><bio xml:lang="ru"><p>Барабанов Василий Сергеевич – бакалавр по направлению "Информационные системы и технологии" (2024)</p><p>Волоколамское шоссе, д. 4, Москва, 125993 </p></bio><bio xml:lang="en"><p>Vasiliy S. Barabanov, Bachelor in Information Systems and Technologies (2024)</p><p>4, Volokolamskoe highway, Moscow 125993 </p></bio><email xlink:type="simple">BarabanovVas2002@gmail.com</email><xref ref-type="aff" rid="aff-1"/></contrib></contrib-group><aff-alternatives id="aff-1"><aff xml:lang="ru"><institution>Московский авиационный институт (национальный исследовательский университет)</institution><country>Россия</country></aff><aff xml:lang="en"><institution>Moscow Aviation Institute (National Research University)</institution><country>Russian Federation</country></aff></aff-alternatives><pub-date pub-type="collection"><year>2025</year></pub-date><pub-date pub-type="epub"><day>11</day><month>03</month><year>2025</year></pub-date><volume>28</volume><issue>1</issue><fpage>17</fpage><lpage>34</lpage><permissions><copyright-statement>Copyright &amp;#x00A9; Коробков М.А., Барабанов В.С., 2025</copyright-statement><copyright-year>2025</copyright-year><copyright-holder xml:lang="ru">Коробков М.А., Барабанов В.С.</copyright-holder><copyright-holder xml:lang="en">Korobkov M.A., Barabanov V.S.</copyright-holder><license xml:lang="ru" license-type="creative-commons-attribution" xlink:href="https://creativecommons.org/licenses/by/4.0/" xlink:type="simple"><license-p>Данная работа распространяется под лицензией Creative Commons Attribution 4.0.</license-p></license><license xml:lang="en" license-type="creative-commons-attribution" xlink:href="https://creativecommons.org/licenses/by/4.0/" xlink:type="simple"><license-p>This work is licensed under a Creative Commons Attribution 4.0 License.</license-p></license></permissions><self-uri xlink:href="https://re.eltech.ru/jour/article/view/967">https://re.eltech.ru/jour/article/view/967</self-uri><abstract><sec><title>Введение</title><p>Введение. Тенденции к миниатюризации электронных устройств в совокупности с увеличением их вычислительных мощностей приводят к повышению плотности трассировки печатных узлов и уменьшению размеров элементов проводящего рисунка: дорожек и зазоров между ними, контактных площадок компонентов и переходных отверстий. Увеличение плотности межсоединений – причина снижения надежности устройств, а также роста брака при производстве. Актуальной задачей является создание способов, которые позволят количественно оценить возможность изготовления заготовок или печатных плат, соответствующих требованиям приемки, в зависимости от параметров их конструкции и характеристик технологического процесса. Поскольку существенную долю дефектов вносит процесс фотолитографии, особо важной является априорная оценка степени дефектности перед изготовлением и определение на основе оценки способов для уменьшения количества дефектов.</p></sec><sec><title>Цель работы</title><p>Цель работы. Разработка и экспериментальная проверка математической модели вероятности выхода годных заготовок печатных плат для процесса фотолитографии.</p></sec><sec><title>Материалы и методы</title><p>Материалы и методы. Проведен анализ причин возникновения дефектов в процессе фотолитографии, на основе которого определены технологические параметры, позволяющие количественно охарактеризовать величину дефекта: искажение размеров проводящего рисунка и неровность края проводника. Предложена математическая модель, описывающая вероятность бездефектного изготовления заготовки. В качестве основных оцениваемых конструкционных параметров печатной платы выбрана ширина проводника и размер зазора между проводниками. Используемые в модели требования к печатной плате определены на основе международных стандартов по их проектированию и приемке.</p></sec><sec><title>Результаты</title><p>Результаты. Разработана методика экспериментальной проверки предложенной вероятностной модели с помощью цифровой обработки и статистического анализа изображений фотошаблонов и заготовок. Подтверждена адекватность модели для лабораторной производственной линии. Для исследуемой операции определены зависимости технологических параметров от проектируемой ширины проводника и проведена корректировка процесса, позволившая увеличить вероятность выхода годных заготовок.</p></sec><sec><title>Заключение</title><p>Заключение. Результаты расчета вероятности, полученные с помощью модели, могут служить индикатором необходимости внесения изменений в конструкцию печатного узла или элементом оценки рисков и размера резервов, требуемых для производства образцов высокой сложности для предприятия-изготовителя.</p></sec></abstract><trans-abstract xml:lang="en"><sec><title>Introduction</title><p>Introduction. The current trend in the production of miniaturized electronic devices with improved computing power and performance leads to an increase in the density of interconnections on printed circuit boards (PCBs) and a reduction in the dimensions of such conductive pattern elements, as tracks and gaps, contact pads of components and vias. At the same time, the growing interconnection density decreases the reliability of devices and increases the number of defects in production. In this connection, the development of approaches to quantitative evaluation of the manufacturability of PCB blanks that meet the acceptance criteria represents a relevant research task. A significant share of defects is introduced at the photolithography stage; therefore, an a priori estimation of the number of defects before fabrication and determination of approaches to their reduction are of particular significance.</p></sec><sec><title>Aim</title><p>Aim. Development and experimental verification of an analytical model for determining the yield probability of PCB blanks of acceptable quality for the photolithography stage.</p></sec><sec><title>Materials and methods</title><p>Materials and methods. An analysis of reasons for emergence of defects in the process of photolithography was conducted. On this basis, the manufacturing parameters that describe the defect value, i.e., conductive pattern distortion and conductor edge roughness, were established. A mathematical model describing the probability of defect-free manufacturing of PCB blanks was proposed. Conductor width and conductor gap size were used as estimated design parameters of PCBs. The quality criteria for the design and acceptance of PCBs were determined based on international standards.</p></sec><sec><title>Results</title><p>Results. A methodology for experimental verification of the proposed probabilistic model by means of processing and statistical analysis of photomask and blank images was developed. Difficulties associated with the creation of datasets and their processing were considered. The adequacy of the model for a laboratory production line was confirmed. For the investigated process, the dependencies of manufacturing parameters on the designed conductor width were determined and the corresponding adjustments of the process were introduced. This allowed the probability of obtaining PCB blanks of acceptable quality to be increased.</p></sec><sec><title>Conclusion</title><p>Conclusion. The results of probability calculations obtained using the proposed model can be used as an indicator of required changes in the design of a printed assembly or for assessing the risks and reserves required by the manufacturer for the production of high-complexity specimens.</p></sec></trans-abstract><kwd-group xml:lang="ru"><kwd>печатные платы</kwd><kwd>надежность электроники</kwd><kwd>оценка надежности</kwd><kwd>фотолитография</kwd><kwd>анализ выхода годных заготовок печатных плат</kwd><kwd>производство печатных плат</kwd></kwd-group><kwd-group xml:lang="en"><kwd>printed circuit boards</kwd><kwd>PCBs</kwd><kwd>electronics reliability</kwd><kwd>reliability estimation</kwd><kwd>photolithography</kwd><kwd>PCB blank yield analysis</kwd><kwd>manufacturing design</kwd></kwd-group></article-meta></front><back><ref-list><title>References</title><ref id="cit1"><label>1</label><citation-alternatives><mixed-citation xml:lang="ru">Influence of Nonfunctional Contact Pads on Printed-Circuit Performance / S. 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