Back-Side Electron-Bombarded Silicon pin-Strip

Introduction. In recent decades, in the field of photoelectronics, special attention has been paid to the development of semiconductor matrix photodetectors. These detectors have become an effective alternative to existing television receiving systems. Among such devices, linear position-sensitive sensors are used in cases where the rapid registration of changes to the environment is required (for instance, high-speed locators for flying vehicles).Aim. To develop a strip of silicon pin-diodes as part of a hybrid IR-detector for effective registration of photoelectrons with time resolution less than 10 ns, as well as to model the key electro-physical characteristics of the strip.Materials and methods. In the device under development, the registration of photoelectrons is achieved by the presence of a near-surface field using p ++–p junction formed by diffusion of boron into the silicon with resistivity of 3 kΩ · cm. The pulling field is also formed in the space charge region between p ++ - and n ++ -regions. Diffusion of phosphorus was carried out to create the n ++ -region. Numerical calculations of potential distribution, concentration of free charge carriers and currents were carried out using software for 1D- and 2D-modelling (SimWin and TCAD Synopsys).Results. 2D-calculation of charge carrier concentration and potential distribution was performed. The study determined the minimum bias for the complete depletion of the i-layer, including that for longitudinal grooves of various depths. The strip was tested as part of a hybrid photoelectric device by irradiating light pulses from IR LED. When the voltage on the diodes was reached –270 V, the duration of the signal front on all channels was 5…9 ns.Conclusion. For use in IR-hybrid detectors, a strip of 12 silicon pin-diodes was developed with a sensitive element of 24 × 0.2 mm in dimension. The study of pulse characteristics showed that the necessary duration of the front signal on all channels was achieved without thinning thus satisfying the requirements for high-speed position-sensitive sensor of the infrared radiation.


Introduction.
In recent decades, special attention has been paid to the development of semiconductor matrix photodetectors in the field of photoelectronics. With the application of microelectronic inquiry and processing systems, these detectors have become an effective alternative to existing analogue television receiving systems [1][2][3][4][5].
Among such devices, emphasis may be placed on linear photodetectors, which are based on a strip of position-sensitive radiation sensors. These sensors are used for rapid (several or tens of nanoseconds) registration of changes in conditions with the corresponding response reaction (for instance, locators of controlled and uncontrolled aircraft).
Matrix semiconductor devices are developed following the steady trend for miniaturisation. However, a decrease in the dimensions of recording pixels is accompanied by an increase in the density of metallic conductors and polysilicon layers, which results in a decrease in the share of the exposed surface of the photodetector. Therefore, the architecture of the photodetector with bombardment from the substrate side free of any metal layout and structural coatings (backside (BS) structures) has recently become a topicof interest [3,6,7].
In such downward-facing structures, holeelectron pairs are generated as a result of absorption of photons (internal photoeffect) bombarding the reverse surface, while electrons move according to the existing potential difference in the direction of the sensitive cells (p-n junctions) on the opposite side. The drawbacks of this design is the rather low energy of the bombarding photons (approximately equal to the width of the band gap of the material), with the result that one photon generates one holeelectron pair. A more advanced device architecture includes a separate photocathode and anode (similar to a photomultiplier) [7,8]. In this case, a separately operating photocathode serves as a detector of incident photons in the required wavelength range, while the BS crystal with a matrix of recording pixels is bombarded by photoelectrons emitted from the photocathode (external photoeffect). Applying an accelerating field between the cathode and anode makes it possible to reach the energy of photoelectrons of several keV. These photoelectrons, while bombarding the surface of the semiconductor p-n-anode, provide generation of hundreds of hole-electron pairs within the bulk of semiconductor, which results in a high multiplication factor of the device [8,9].
Structure of the fabricated strip of silicon pinphotodetectors. The works were aimed to develop a strip of Si pin-diodes for the hybrid IR detector, which should provide effective registration of photo-electrons with energy 1…5 keV and have time resolution better than 10 ns. Silicon of p-type conductivity was used as the base, since electrons (minority charge carriers in p-Si) are more mobile than holes. The electrical resistivity of the crystal was 3000 Ohm.cm [10].
Currently produced silicon detectors provide registration of electrons within the energy range from 200…600 eV (energy threshold of registration) to tens of keV and higher. During the interaction of high-energy electrons with solid-state detectors, multiple elastic and non-elastic scatterings of electrons occur in the crystal lattice [11,12], resulting in change in their motion paths and generating the possibility of releasing a portion of the electrons from the solid-state body to vacuum following several scatterings within the subsurface area. This specific feature of electron scattering requires the thickness of the surface layers of the solid-state detector, where no effective collection of non-majority charge carriers occurs, to be minimised. These layers include dielectric passivation layers, layers providing minimisation of surface resistance and subsurface areas of p-n or isotype junctions. The thickness of such layers typically does not exceed 10 nm [13,14].
The structure of layers for the developed device is presented in Fig. 1, a. The effective registration of electrons having energy of about 2 keV is provided at the expense of the subsurface field via the use of the p ++ -p-isotype junction, which has been realised by boron diffusion with the surface concentration of approximately 20 3 10 cm .
 Boron diffusion was performed using the Chemical Vapour Deposition (CVD) method at temperature of 900 °C. The pulling field, in turn, is also formed in the space charge region between the p ++ -and n ++ -regions. Phosphorous diffusion at the temperature of 950 °C was carried out to create the n ++ -region. The boron impurity profile ( Fig. 1, b) was measured usingthe secondary-ion mass spectrometry (SIMS) method (the region of concentrations, which are beyond the measurability of this method, is shown by the dotted line). As follows from this figure, boron concentration decreases exponentially in the direction from the surface to the depth layers of the sample. The boron diffusion depth may be estimated as being approximately equal to 50 nm. As was shown by SIMS measurements, the n ++ -pjunction realised by phosphorous diffusion was located at a depth of about 1600 nm.
The manufactured samples were characterised by the following parameters: total number of elements in the strip -12; total number of elements in the strip -2 × 0.2 mm; sizes of the sensitive region -24 × 0.2 mm. The structure of the active area of electronsensitive silicon diodes and its cross-section are presented in Fig. 2 (three elements are shown). Bombardment with electrons is realised from the p ++ -layer side. The registered particles are absorbed in the region of the p ++ -p-junction and the high-resistivity base of p-type, moving to the p-n ++ -junction in driftmode provided by the reverse bias. A reduction of the initial thickness of the middle part of the silicon strip (350 μm) to 50 μm may be applied in order to decrease the time for collecting electrons from the base. The width of the groove was equal to 200 μm. The reduction in thickness also results in an improvement of the frequency-contrast characteristics of the photodetector. However, a semiconductor with a thickness of less than 250 μm cannot be used due to the fragility of the silicon plate.
At the first stage, the SiO2 layer was deposited on the strip side opposite to the one being bombarded; next, the n ++ -polysilicon layer was deposited into the photolithographic processed window [10]. The width of the poly-Si layer was also equal to 200 μm. Subsequently, an aluminium contact was created on the polysilicon. The distance between the elements was determined by the distance between the adjacent windows -that is, 60 μm. The upper p ++ -layer was solid. Aluminium was also deposited on this layer, with the subsequent opening of the window opposite to n ++ -polysilicon. The bottom of the groove should be free from aluminium. A negative bias of 200…300 V was applied to the upper electrode in order to create the pulling field in the i-region of the diodes.
Further, the electrophysical properties of the silicon strip of photodetectors, bombarded by electrons from back-side, are analysed.
Calculation of the characteristics of the silicon pin-photodetectors strip. Let us estimate the bias, which should be applied between the p ++ -and n ++regions of the structure for complete depletion of the i-layer. As a first approximation, the equation de- scribing the width of the space-charge region (SCR) for the abrupt p-n-junction will be used [15]: where 11.9  relative dielectric permittivity of silicon; 0 electric permittivity of vacuum; bi Ubuilt-in potential; Uapplied voltage bias; eelectron charge; Nconcentration of charge carriers.
The space charge region is formed by the immobile impurity ions and develops following the root law with increased applied bias. The electrical resistivity was converted into carrier concentration using reference data [15]. For silicon at the temperature of 300 K, it was assumed that all impurity is ionised.
The results of calculation of SCR width in silicon, which is used as a pin-photodetector, have shown that low-doped silicon, having the electrical resistivity of 3 kOhm cm,    will be completely depleted at a voltage of 300 V, while for 2 kOhm cm    at the same voltage, it will be depleted to the depth of 245 nm. Due to their lower carrier concentration, substrates of n-type having the same electrical resistivity will be characterised by a substantially greater SCR width [15]. In the case of complete depletion, the calculated capacitance of the structure having the specified parameters will not exceed 2 pF. Such a capacitance should provide the required data for the time resolution in the applied bias scheme.
The presented estimation is characterised by a large error since SCR in a semiconductor does not have sharp boundaries and its edge does not have an exact position due to Coulomb screening with mobile electrons. The width of this smearing is characterised by the Debye screening length [15,16]: In low-doped silicon (with concentration  13 3 10 cm p   at room temperature, D L will be equal to several microns, i.e. depletion in the actual device will appear much earlier. Using the one-dimensional simulation software SimWin [17], the authors fulfilled the calculation of free charge carriers and potential in the studied pin-structure at different applied voltages. The semiconductor parameters necessary for calculation (the thickness of layers and the impurity concentration) correspond to those shown in Fig. 1. The n ++ -ptransition is considered as quite sharp, while the impurity concentration profile in the p ++ -layer is approximated by an exponent. The calculation was performed for the groove section, where the thickness of the whole structure is equal to 150 μm.
In the case of absence of bias, the SCR occupies less than 15 μm in the structure. The application of reverse bias results in SCR expansion and appearing of an electric field and small reverse current in it. At 100 V, U  the SCR expanded almost within the whole structure. Its boundary appears to be localised within the range of 139…149 μm (Fig. 3). The electric field occupies the whole structure, creating the pulling field for the charge carriers; the electric field strength varies in the range from 2 1.7 ·10 to 4 1.3·10 cm. As follows from (1), the SCR width increases sublinearly with the growth of U; thus, for the depletion of the structure of 350 μm in thickness, the bias of about 300 V should be applied.
The current-voltage characteristic of the pindiode, calculated in the one-dimensional approach, was characterised by the monotonic increase in the density of the reverse current up to the value of 2 90mA cm at voltage of -100 V. The 3D calculation of the structure aimed at more complete characterisation of the pin-diode strip was performed using the TCAD Synopsys simulation software package. The Structure Editor subprogram was used for creation of a 3D model of the strip (Fig. 4). However, the detailed 3D model calculations necessitated very large memory, which were not supported by the software package. This was caused by a large size of the structure, on the one hand, and by the availability of extremely thin highdoped layers, which required the application of a very detailed grid, on the other hand. Therefore, all calculations were performed under the quasi-twodimensional approach. After applying a section both across the structure and along it (one of these sections is presented in Fig. 4, C1), two new 2D models were created. The position of sections was varied.
Cross-section of the structure. Potential distributions in the cross-section of the structure for different groove depths d and applied voltage U are presented in Fig. 5. From the performed analysis, it follows that the potential at the bottom of the shallow groove is nearly equal to that applied to the metallic electrode at the sur- However, if the groove is sufficiently deep, then even a p ++layer having a concentration exceeding 20 3 10 cm  will not provide equipotentiality; in this case, the bottom of the groove will be exposed to only half of the bias applied to the structure (Fig. 5 In this case, the groove itself insignificantly modifies the potential pattern of the structure, which is primarily created by the metallic contacts, resulting in the groove appearing to be "submerged" into the existing electric field.
The two-dimensional distribution of the space charge region of the pin-structure is characterised by the cylindrical shape over the metallic contact tracking isopotential curves in Fig. 5. In the vertical section, the potential is distributed between the metallic contact and the groove following the quadratic law, while the strength of the electric field follows the linear law.
The specific current density between the metallic contact and the groove is approximately equal to 2 4 mA cm . Longitudinal section of the structure. Calculations of the electric field and the charge distribution in the longitudinal section were performed. Here, the subject of analysis was the distribution of the electric field in semiconductor between the metallic contacts and its dependence on the distance between the contacts. The effect of this distance on the joining of SCR of the adjacent diodes was additionally investigated.
The geometrical parameters and doping corresponded to those shown in Fig. 5, b: the groove depth 200 m, d  the distance between the metallic contacts is 60 μm. The bias was equal to 130 V (the zero potential was located on the metallic contact). The potential distribution below the groove, which is presented in Fig. 6, a, is generally uniform for the most part of the structure depth. Non-uniformity becomes essential only for the last 20 μm. As follows from the plot, in the middle between the contacts the potential is equal to -30 V.
The distribution of the electric field along the vertical line of the structure is presented in Fig. 6, b. As could be expected, maximum deviation from the uniform distribution of the electric field was detected at the edges of the contacts, where it amounts to 4 2.5 10 V cm  for the specified value of the applied voltage. In this case, the field in the opened from contact surface is 5 times lower.
The distribution of the total specific current density in the structure at the reverse bias of 130 V is presented in Fig. 7. In the region that is closed by the contacts, the current density is uniform, being equal In the central part, the current is one order less and is shifted to the edges of the metallic contacts. Current-voltage characteristics for several metallic contacts with the sizes of 0.3 × 0.2 μm have been calculated.
The potential distribution was then compared along the structure at varying distance between the metallic contacts from 40 to 80 μm. Within the specified limits, the potential in the central part between the contacts varied from -20 to -40 V, while a decrease in the electric field strength was minorfrom 3 5 10  to An increase in the width of the intercontact gap up to 80 μm results in the substantial redistribution of the current density from its center to the metallic contacts. In the region between the contacts, the current density is less along the whole thickness of the structure, which should be considered as non-optimal.
It is worth bearing in mind that the bottom of the deep groove is exposed to only part (half in the case of 200 m d  ) of the difference of potential applied to the structure (between the upper and lower metallic contacts, refer to Fig. 5, b). In taking this circumstance into account, the bottom of the groove should be exposed to the corresponding reduced potential (Fig. 8, a). The principal result is that the SCR width does not extend along the whole distance of 150 μm. About 25 μm under the groove remain in the electri- cal neutrality region (the SCR boundary is shown by the white line). In this case, the distance between the lower metallic contacts slightly affects the SCR width and its certain "deflection" in the case of the large gap (80 μm) should be considered as insignificant.
The distribution of the current density in the groove region, keeping in mind the reduced potential at the groove bottom comparatively to that applied to the metallic contact (Fig. 8, b), in general is similar to the previously presented plots (Fig. 7) and differs only by slightly reduced values. A decrease in the current density is observed between the lower metallic contacts.
For the developed fast-response displacement sensor, the response rate of the definite diode is an important parameter. It is defined by the time of the drift of an electron through the structure and is directly proportional to the length of the flight L: , the strength of the electric field). Based on different reference data, the electron mobility in silicon was adopted equal to   2 0.14 0.19 m V s .  Thus, at bias 300 V, U  the flight time through the structure for the thickness of d = 350 μm will be equal to 2.7 ns, and for the thickness of 150 μmhalf as much.
Tests of the hybrid pin strip-based IR device. After the manufacturing of series diode strips without grooves, the samples were tested within the integrated hybrid photodetector; the front duration was determined pursuant to GOST 11612.13-85. In these measurements, the photocathode of the device was illuminated by light pulses emitted by an LED with wavelength of 1310 nm, which was located at dis-tance of 1 cm from the detector input window. The LED was powered, by voltage pulses 3 V of negative polarity from the G5-56 generator. The parameters were as follows: frequency of emitted light pulses -2 Hz; generator pulse width -10 ns; pulse rise and droop -5 ns each. A high voltage pc 2.6 kV U  relative to the diode strip was applied to the photocathode via ballast resistance b 25 GOhm R  . In the performed experiments, the effective area of the photocathode opposite the diode strip was limited by a 2 × 25 mm diaphragm mounted directly on the detector window. During the study of any diode, other diodes within the strip were grounded. The distance between the elements was equal to 60 μm. The common electrode of the strip was powered from a DC power supply with voltage d U of negative polarity; the DC dark current d I in the circuit was measured by a microammeter. The power supply regime for all diodes was d 270 V, U  meanwhile the results of the performed analysis evidenced that the whole structure was depleted. This bias was somewhat below the calculated one for the studied thickness of the active area of the photodetector. This was caused by the previously discussed Debye tailing of the SCR edge, as well as by existence of the diffusion "tails" from the highly doped layers, which effectively decreased the SCR width.
The response oscillogram for one of the diodes on the IR LED pulsed signal is presented in Fig. 9. The response is shown after the elimination of noise; the frequency band -150 MHz, the circuit load -50 Ohm. As seen, the front of the registered signal is about 5 ns. In general, the results of investigations have has been achieved for all channels of the device (5…9 ns). This result demonstrates that at the first stage of engineering design, the thinning of the central part of the photodetector may be not applied in order not to complicate the technology of the device production. Nevertheless, taking the aforementioned calculationsinto account, we believe that the development of technological operations aimed at the precision thinning of the photosensitive region of the IR detector will allow a substantial (up to 3 times) decreasein the applied operating bias to be realised along with a corresponding threefold increase in the speed of response of the photosensitive strip.
Conclusion. A strip consisting of 12 silicon pindiodes characterised by the crystal electric resistivity of 3 kOhm . cm has been developed for a hybrid IR photodetector having sensitivity in the spectral range of 1…1.6 μm. Highly doped nanoscale p ++ -and n ++ -layers were created by diffusion of boron and phosphorous. The dimensions of the sensitive area of the strip element were 24 × 0.2 mm. In the space charge region of the structure, the pulling field was formed due to the applied reverse bias.
A 2D calculation of charge carrier concentration and potential distribution in the pin-structure was carried out. The minimum biases providing complete depletion of the i-layer were determined, including for the case of additionally created longitudinal grooves of various depths. It was demonstrated that varying the distance between the metallic contacts in the range from 40 to 80 μm resulted in a change in potential between these contacts in the range from -20 to -40 V, while the strength of the electric field decreased only slightly.
The fabricated strip was tested within the integrated hybrid photoelectric device using illumination by 10 ns light pulses emitted by IR LED with wavelength of 1310 nm. Photoelectrons emitted from the photocathode were accelerated in a high voltage of 2.6 kV relative to the pin-diode strip and detected by definite diodes within the strip. During tests, the device sustained voltage up to pc 3.5 kV, U  while the diodes were able to sustain a pulse current of 150 μA and even more. The results of investigations of the pulse characteristic have shown that without a thinning operation and with the bias at the diode of -270 V. the signal front time for all channels varied in the range 5…9 ns, thereby satisfying the requirements for a fastresponse, position-sensitive IR emission sensor.

Authors' Contribution
Mikhail R. Ainbund, introduction to the problem; formulation of the problem; discussion of the results. Andrey V. Nikolaev, the formation of heavily doped p ++ -and n ++ -layers by diffusion; optimization and description of technological regimes.